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TAS2020 Datasheet(PDF) 6 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 79 page  THERMAL METRIC(1) Standard JEDEC(2) UNIT HR-QFN 26 PINS ΨJB Junction-to-board characterization parameter 15.2 ℃/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) JEDEC Standard 4 Layer PCB 5.5 Electrical Characteristics TA = 25°C, PVDD = 5V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AMPLIFIER PERFORMANCE POUT_EXT _PVDD Maximum Output Power - 1% THD+N RL = 8Ω + 33 µH 1.8 W RL = 4Ω + 33 µH 3.2 W ηSYSTEM_ EXT_1W System Efficiency at POUT = 1.0W RL = 8Ω + 33 µH 91 % RL = 4Ω + 33 µH 89 % ηSYSTEM_ EXT_MAX_ POUT System Efficiency at 1% THD+N power Level RL = 8Ω + 33 µH 93.5 % RL = 4Ω + 33 µH 90.4 % VN_EXT Idle channel Noise A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.2 µV DNR_EX T Dynamic Range A-Weighted, -60dBFS Method, RL = 8Ω + 33 µH 114.4 dB THD+N_ EXT Total Harmonic distortion + Noise POUT = 1W, RL = 8Ω + 33 µH 0.003 % POUT = 1W, RL = 4Ω + 33 µH 0.004 % KCP_EXT Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8Ω + 33 µH, Input = Digital Silience –68 dBV VOS_EX T Output Offset Voltage Idle channel –1 1 mV PSRRPV DD_EXT PVDD power-supply rejection ratio PVDD + 200mVpp, fripple = 217Hz 119 dB PVDD + 200mVpp, fripple = 1kHz 115 dB PVDD + 200mVpp, fripple = 20kHz 91 dB PSRRVD D_EXT VDD power-supply rejection ratio VDD + 200mVpp, fripple = 217Hz 113 dB VDD + 200mVpp, fripple = 1kHz 113 dB VDD + 200mVpp, fripple = 20kHz 91 dB TDM Serial Port PCM Sample Rates and FSYNC Input Frequency 16 192 kHz SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz SBCLK Maximum Input Jitter RMS Jitter below 40kHz that can be tolerated without performance degradation 0.5 ns RMS Jitter above 40kHz that can be tolerated without performance degradation 5 ns SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 6 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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