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TAS2020 Datasheet(PDF) 8 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 79 page  TA = 25°C, PVDD = 5V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 0.1 uA VDD, SDZ=0 0.2 uA IOVDD, SDZ=0 0.1 uA IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 0.1 uA VDD, All clocks Stopped 12 uA IOVDD, All clocks Stopped 0.1 uA IQ_NG Current consumption in Idle channel with noise gate PVDD, POUT = 0, Noise gate enabled 0.1 mA VDD, POUT = 0, Noise gate enabled 2.2 mA IOVDD, POUT = 0, Noise gate enabled 0.1 mA IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA VDD, POUT = 0, Noise gate disabled 5.6 mA IOVDD, POUT = 0, Noise gate disabled 0.1 mA DIGITAL IOs VIH High-level digital input logic voltage threshold All digital pins 0.7x IOVDD V VIL Low-level digital input logic voltage threshold All digital pins 0.3x IOVDD V VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD - 0.2V V VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2x IOVDD V VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V IIH (1) Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA IIL (1) Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ (1) Errata: Additional 2mA to 3mA current consumption expected if IRQZ signal is pulled high. Read more details in section "what to do and what not to do". 5.6 Timing Requirements TA = 25°C, VDD = IOVDD = 1.8V (unless other wise noted) MIN NOM MAX UNIT I2C - Standard Mode fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW LOW period of the SCL clock 4.7 μs tHIGH HIGH period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 μs tSU;DAT Data set-up time 250 ns tr SDA and SCL rise time 1000 ns TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 8 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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