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TAS2020 Datasheet(PDF) 49 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 79 page  Table 7-36. INT_LATCH_2 Register Field Descriptions (continued) Bit Field Type Reset Description 4 INT_LTCH2[4] R 0h Interrupt due to PLL clock error 0h = No interrupt 1h = Interrupt 3 INT_LTCH2[3] R 0h Interrupt due to tdm error 0h = No interrupt 1h = Interrupt 2 INT_LTCH2[2] R 0h Interrupt due to ratio change error flag 0h = No interrupt 1h = Interrupt 1 INT_LTCH2[1] R 0h Interrupt due to fs change error flag 0h = No interrupt 1h = Interrupt 0 INT_LTCH2[0] R 0h Interrupt due to invalid ratio fs flag 0h = No interrupt 1h = Interrupt 7.1.36 INT_LATCH_3 Register (Address = 63h) [Reset = 00h] Return to the Summary Table. This register provides the status of latched interrupts. Table 7-37. INT_LATCH_3 Register Field Descriptions Bit Field Type Reset Description 7 INT_LTCH3[7] R 0h Interrupt due to over temperature detected 0h = No interrupt 1h = Interrupt 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 INT_LTCH3[3] R 0h Interrupt due to Class-D Over current protection 0h = No interrupt 1h = Interrupt 2 INT_LTCH3[2] R 0h Interrupt due to Over voltage on PVDD supply. 0h = No interrupt 1h = Interrupt 1 RESERVED R 0h Reserved 0 RESERVED R 0h Reserved 7.1.37 INT_LATCH_4 Register (Address = 64h) [Reset = 00h] Return to the Summary Table. This register provides the status of latched interrupts. Table 7-38. INT_LATCH_4 Register Field Descriptions Bit Field Type Reset Description 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 RESERVED R 0h Reserved 2 INT_LTCH4[2] R 0h Interrupt due to clock halt flag 0h = No interrupt 1h = Interrupt www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TAS2020 |
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