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TAS2020 Datasheet(PDF) 39 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 79 page  Table 7-10. TDM_CFG1 Register Field Descriptions (continued) Bit Field Type Reset Description 0 RX_EDGE R/W 0h TDM RX capture clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK 7.1.10 TDM_CFG2 Register (Address = 9h) [Reset = 0Ah] Return to the Summary Table. This register configures device TDM modes. Table 7-11. TDM_CFG2 Register Field Descriptions Bit Field Type Reset Description 5-4 RX_SCFG[1:0] R/W 0h TDM RX time slot select config. 0h = Mono with time slot equal to I2C address offset 1h = Mono left channel 2h = Mono right channel 3h = Stereo downmix (L+R)/2 3-2 RX_WLEN[1:0] R/W 2h TDM RX word length. 0h = 16 bits 1h = 20 bits 2h = 24 bits 3h = 32 bits 1-0 RX_SLEN[1:0] R/W 2h TDM RX time slot length. 0h = 16 bits 1h = 24 bits 2h = 32 bits 3h = Reserved 7.1.11 TDM_CFG3 Register (Address = Ah) [Reset = 10h] Return to the Summary Table. This register configures device TDM modes. Table 7-12. TDM_CFG3 Register Field Descriptions Bit Field Type Reset Description 7-4 RX_SLOT_R[3:0] R/W 1h TDM RX Right Audio Channel Time Slot. 3-0 RX_SLOT_L[3:0] R/W 0h TDM RX Left Audio Channel Time Slot. 7.1.12 TDM_CFG5 Register (Address = Ch) [Reset = 13h] Return to the Summary Table. This register configures device TDM modes. Table 7-13. TDM_CFG5 Register Field Descriptions Bit Field Type Reset Description 7 TX_KEEPCY R/W 0h TDM TX SDOUT LSB data will be driven for 0h = full-cycle 1h = half-cycle 6 TX_KEEPLN R/W 0h TDM TX SDOUT will hold the bus for the following when TX_KEEPEN is enabled 0h = 1LSB cycle 1h = always www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TAS2020 |
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