TAS2020 datasheet(71/79 Pages) TI2

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8.2.2 Detailed Design Procedure

8.2.2.1 Mono/Stereo Configuration

In this application, the device is assumed to be operating in mono mode. See Section 6.5.2 for information

on changing the I2C address of the TAS2020 to support stereo or multi-channel operation. Mono or stereo

configuration does not impact the device performance.

8.2.2.2 EMI Passive Devices

The TAS2020 supports edge-rate control to minimize EMI, but the system designer can want to include passive

devices on the Class-D output for further reduction in EMI . These passive devices that are labeled L2, L3, C10

and C11 in Section 8.2. If C10 and C11 are used, L2 and L3 must also be installed, and C10 and C11 must be

placed after L2 and L3 respectively to maintain the stability of the output stage.

The component value selection for the EMI filters depends on the application need on the frequency band that

needs to be suppressed using these filters. Higher cutoff frequency helps in reducing the BOM size and reduces

the switching power loss associated with the filters. Application must select the highest cutoff frequency filter

which meets the system's frequency suppression target to get better efficiency performance.

The DC resistance of the inductors or ferrite beads used in the EMI filters also plays a critical role in system

efficiency. Lower resistance reduces power loss and helps in improving overall system efficiency. Based on

available board space, smallest DC resistance components which meet the application needs and gives better

efficiency performance.

8.2.2.3 Miscellaneous Passive Devices

The GREG Capacitor requires 100nF to meet Class-D power delivery and efficiency specs. For device

functionality, the GREG capacitor should be kelvin/star connected to PVDD pin of the device.

In order to maintain the device performance and keep the supply ripple within the device specification,

minimizing the parasitic inductance on supply/ground paths for decoupling capacitors is required. All supply

decapacitors should be selected as smallest package footprint to minimize the ESL of the capacitors. The layout

placement and routing of the capacitors is critical for minimizing the trace parasitic inductance. Refer to Layout

section (Section 8.5.1) to get detailed recommendations.

8.2.3 Application Performance Plots

TA = 25℃, PVDD = 5V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33μH, Fin = 1kHz, Fs = 48kHz, Gain = 12dBV,

SDZ=1, Noise gate mode disabled, Measured on EVM with typical application use case (Section 8.2). Measured

filter free with an Audio Precision with a 22Hz to 20kHz un-weighted bandwidth, unless otherwise noted.

Output Power (W)

0.001

0.01 0.02 0.05 0.1 0.2

0.5

2 3 4 5

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

PVDD = 2.5 V

PVDD = 3.6 V

PVDD = 4.4 V

PVDD = 5 V

PVDD = 5.5 V

Figure 8-2. THDN vs Output Power

Output Power (W)

0.001

0.005

0.02

0.05 0.1 0.2

0.5

2 33.5

100

PVDD = 2.5 V

PVDD = 3.6 V

PVDD = 4.4 V

PVDD = 5 V

PVDD = 5.5 V

Figure 8-3. Efficiency vs Output Power

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TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

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