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TAS2020 Datasheet(PDF) 9 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 79 page  TA = 25°C, VDD = IOVDD = 1.8V (unless other wise noted) MIN NOM MAX UNIT tf SDA and SCL fall time 300 ns tSU;STO Set-up time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs Cb Capacitive load for each bus line 400 pF I2C - Fast Mode fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW LOW period of the SCL clock 1.3 μs tHIGH HIGH period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 0.6 μs tHD;DAT Data hold time: For I2C bus devices 0 0.9 μs tSU;DAT Data set-up time 100 ns tr SDA and SCL rise time 20 + 0.1 × Cb 300 ns tf SDA and SCL fall time 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs Cb Capacitive load for each bus line 400 pF TDM Port fsbclk SBCLK Frequency range 0.384 24.576 MHz tH(SBCLK) SBCLK high period 0.35/fsbclk ns tL(SBCLK) SBCLK low period 0.35/fsbclk ns tSU(FSYNC) FSYNC setup time 8 ns tHLD(FSYNC) FSYNC hold time 8 ns tSU(SDIN) SDIN setup time 8 ns tHLD(SDIN) SDIN hold time 8 ns td(SBCLK- SDOUT) SBCLK to SDOUT delay : 10% of SBCLK falling edge or 90% of SBCLK rising edge to 50% of SDOUT, IOVDD=1.8V 30 ns td(SBCLK- SDOUT) SBCLK to SDOUT delay : 10% of SBCLK falling edge or 90% of SBCLK rising edge to 50% of SDOUT, IOVDD=3.3V 18.5 ns tr(SBCLK) SBCLK rise time : 10% - 90% Rise Time 0.15 / fsbclk ns tf(SBCLK) SBCLK fall time : 90% - 10% Rise Time 0.15 / fsbclk ns tf(SBCLK- CLH) SBCLK to CLH delay: Boost share configuration 1 /2* fsbclk ns 5.7 Timing Diagrams tBUF STO STA th(STA) tLOW tr th(DAT) tf tHIGH tsu(DAT) SDA SCL tsu(STA) STA th(STA) STO tsu(STO) Figure 5-1. I2C timing diagram www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TAS2020 |
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