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AT89C51ID2-RDTIM Datasheet(PDF) 87 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 87 Page - ATMEL Corporation |
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87 / 159 page  87 AT89C51ID2 4289A–8051–09/03 Figure 33. Format and State in the Master Transmitter Mode SSLA WA Data A P 08h 18h 28h MT SSLA W AP AP R MR 10h 20h 30h A or A continues 38h 38h A continues 68h Other master Other master 78h B0h To corresponding states in slave mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data Arbitration lost in slave address or data byte Arbitration lost and addressed as slave byte A or A continues Other master Data A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus |
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