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AT89C51ID2-RDTIM Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 159 page ![]() 21 AT89C51ID2 4289A–8051–09/03 –F CLK CPU and FCLK PERIPH, for CKRL<>0xFF In X2 Mode: In X1 Mode: Timer 0: Clock Inputs Figure 3. Timer 0: Clock Inputs Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock. F CPU F = CLKPERIPH F OSCA 2 255 CKRL – () × ----------------------------------------------- = F CPU F = CLKPERIPH F OSCA 4 255 CKRL – () × ----------------------------------------------- = SCLKT0 1 0 FCLK PERIPH :6 T0 pin Sub Clock C/T 1 0 OSCCON TMOD Gate INT0 TR0 Timer 0 Control |
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