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AT89C51ID2-RDTIM Datasheet(PDF) 97 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 97 Page - ATMEL Corporation |
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97 / 159 page  97 AT89C51ID2 4289A–8051–09/03 Table 74. SSADR (096h) - Synchronus Serial Address Register (read/write) Table 75. SSADR Register - Reset value = FEh 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 72. SSCS (094h) read - Synchronous Serial Control and Status Register 7654321 0 SC4 SC3 SC2 SC1 SC0 0 0 0 Table 73. SSCS Register: Read Mode - Reset Value = F8h Bit Number Bit Mnemonic Description 0 0 Always zero 1 0 Always zero 2 0 Always zero 3SC0 Status Code bit 0 See to Table 69. 4SC1 Status Code bit 1 See to Table 69. 5SC2 Status Code bit 2 See to Table 69. 6SC3 Status Code bit 3 See to Table 69. 7SC4 Status Code bit 4 See to Table 69. 7654321 0 A7 A6 A5 A4 A3 A2 A1 A0 Bit Number Bit Mnemonic Description 7 A7 Slave Address bit 7 6 A6 Slave Address bit 6 5 A5 Slave Address bit 5 4 A4 Slave Address bit 4 3 A3 Slave Address bit 3 2 A2 Slave Address bit 2 1 A1 Slave Address bit 1 Bit Number Bit Mnemonic Description |
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