AT89C51ID2-RDTIM datasheet(31/159 Pages) ATMEL

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AT89C51ID2

4289A–8051–09/03

Registers

Table 23. AUXR Register

AUXR - Auxiliary Register (8Eh)

Reset Value = XX00 10’HSB. XRAM’0b

Not bit addressable

7654

3210

XRS2

XRS1

XRS0

EXTRAM

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5M0

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock

periods (default).

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock

periods.

4XRS2

XRAM Size

XRS2XRS1XRS0XRAM size

0256 bytes

1512 bytes

0768 bytes(default)

11024 bytes

01792 bytes

3XRS1

2XRS0

1EXTRAM

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

(HSB), default setting, XRAM selected.

0AO

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AT89C51ID2-RDTIM Datasheet(PDF) 31 Page - ATMEL Corporation

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