AT89C51ID2-RDTIM datasheet(94/159 Pages) ATMEL

94 / 159 page

AT89C51ID2

4289A–8051–09/03

Figure 36. Format and State in the Slave Transmitter Mode

SSLA

Data

P or S

A8h

B8h

C0h

P or S

C8h

All 1’s

B0h

Data

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

Reception of the

own slave address

and one or more

data bytes

Arbitration lost as master

and addressed as slave

Last data byte transmitted.

Switched to not addressed

slave (AA=0)

Table 68. Status in Slave Transmitter Mode

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

Application Software Response

Next Action Taken By 2-wire Software

To/from SSDAT

To SSCON

STA

STO

A8h

Own SLA+R has been

received; ACK has been

returned

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

B0h

Arbitration lost in SLA+R/W as

master; own SLA+R has been

received; ACK has been

returned

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

B8h

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK

will be received

Data byte will be transmitted and ACK will be

received

AT89C51ID2-RDTIM Datasheet(PDF) 94 Page - ATMEL Corporation

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