AT89C51ID2-RDTIM datasheet(103/159 Pages) ATMEL

103 / 159 page

103

AT89C51ID2

4289A–8051–09/03

Figure 40. Data Transmission Format (CPHA = 0)

Figure 41. Data Transmission Format (CPHA = 1)

Figure 42. CPHA/SS Timing

As shown in Figure 40, the first SCK edge is the MSB capture strobe. Therefore the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each byte transmitted (Figure 42).

Figure 41 shows an SPI transmission in which CPHA is’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 42). This format may be preffered in systems having only one Master and

only one Slave driving the MISO data line.

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

567

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

AT89C51ID2-RDTIM Datasheet(PDF) 103 Page - ATMEL Corporation

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