AT89C51ID2-RDTIM datasheet(120/159 Pages) ATMEL

120 / 159 page

120

AT89C51ID2

4289A–8051–09/03

Table 89. Default Values

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 89 and Table 92.

To assure code protection from a parallel access, the HSB must also be at the required

level.

Table 90. Software Security Byte

The two lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown to Table 92.

Mnemonic

Definition

Default value

Description

SBV

Software Boot Vector

FCh

HSB

Copy of the Hardware security byte

101x 1011b

BSB

Boot Status Byte

0FFh

SSB

Software Security Byte

FFh

Copy of the Manufacturer Code

58h

ATMEL

Copy of the Device ID #1: Family Code

D7h

C51 X2, Electrically Erasable

Copy of the Device ID #2: memories size

and type

ECh

AT89C51ID2 64KB

Copy of the Device ID #3: name and

revision

EFh

AT89C51ID2 64KB, Revision

Table 91.

7654

3210

------

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

1-0

LB1-0

User Memory Lock Bits

See Table 92

AT89C51ID2-RDTIM Datasheet(PDF) 120 Page - ATMEL Corporation

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