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H8/3006 Datasheet(PDF) 34 Page - Renesas Technology Corp |
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H8/3006 Datasheet(HTML) 34 Page - Renesas Technology Corp |
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34 / 796 page  1. Overview Rev.5.00 Sep. 12, 2007 Page 6 of 764 REJ09B0396-0500 1.2 Internal Block Diagram Figure 1.1 shows an internal block diagram. Data bus Port 4 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P9 /SCK / IRQ P9 /SCK / IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD 5 4 3 2 1 0 1 0 1 0 1 0 5 4 Port 7 Port A CS0/P84 ADTRG/CS1/IRQ3/P83 CS2/IRQ2/P82 CS3/IRQ1/P81 RFSH/IRQ0/P80 MD2 MD1 MD0 EXTAL XTAL STBY RES RESO NMI H8/300H CPU Interrupt controller DMA controller (DMAC) Serial communication interface (SCI) 3 channels × Watchdog timer (WDT) Address bus Data bus (upper) Data bus (lower) AS RD HWR LWR φ/P67 BACK/P62 BREQ/P61 WAIT/P60 RAM 16-bit timer unit 8-bit timer unit A/D converter D/A converter Programmable timing pattern controller (TPC) Port B Figure 1.1 Block Diagram |
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