H8SLASH3006 datasheet(25/796 Pages) RENESAS

25 / 796 page

Rev.5.00 Sep. 12, 2007 Page xxv of xxviii

REJ09B0396-0500

15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 518

15.2.3 A/D Control Register (ADCR) ............................................................................ 520

15.3

CPU Interface.................................................................................................................... 522

15.4

Operation........................................................................................................................... 523

15.4.1 Single Mode (SCAN = 0)..................................................................................... 523

15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 525

15.4.3 Input Sampling and A/D Conversion Time.......................................................... 527

15.4.4 External Trigger Input Timing ............................................................................. 528

15.5

Interrupts ........................................................................................................................... 528

15.6

Usage Notes ...................................................................................................................... 529

Section 16 D/A Converter................................................................................................. 535

16.1

Overview........................................................................................................................... 535

16.1.1 Features ................................................................................................................ 535

16.1.2 Block Diagram ..................................................................................................... 536

16.1.3 Pin Configuration................................................................................................. 536

16.1.4 Register Configuration......................................................................................... 537

16.2

Register Descriptions ........................................................................................................ 537

16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 537

16.2.2 D/A Control Register (DACR) ............................................................................ 538

16.2.3 D/A Standby Control Register (DASTCR) .......................................................... 539

16.3

Operation........................................................................................................................... 540

16.4

D/A Output Control .......................................................................................................... 541

Section 17 RAM .................................................................................................................. 543

17.1

Overview........................................................................................................................... 543

17.1.1 Block Diagram ..................................................................................................... 543

17.1.2 Register Configuration......................................................................................... 544

17.2

System Control Register (SYSCR) ................................................................................... 544

17.3

Operation........................................................................................................................... 545

Section 18 Clock Pulse Generator .................................................................................. 547

18.1

Overview........................................................................................................................... 547

18.1.1 Block Diagram ..................................................................................................... 547

18.2

Oscillator Circuit............................................................................................................... 548

18.2.1 Connecting a Crystal Resonator........................................................................... 548

18.2.2 External Clock Input ............................................................................................ 550

18.3

Duty Adjustment Circuit ................................................................................................... 552

18.4

Prescalers .......................................................................................................................... 552

18.5

Frequency Divider............................................................................................................. 552

H8/3006 Datasheet(PDF) 25 Page - Renesas Technology Corp

H8/3006 Datasheet(HTML) 25 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL