H8SLASH3006 datasheet(10/796 Pages) RENESAS

10 / 796 page

Rev.5.00 Sep. 12, 2007 Page x of xxviii

REJ09B0396-0500

Item

Page

Revision (See Manual for Details)

9.4.6 Setting Initial

Value of 16-Bit Timer

Output

Figure 9.32 Example of

Timing for Setting Initial

Value of 16-Bit Timer

Output by Writing to

TOLR

333

Figure amended

TOLR address

Address bus

TOLR

16-bit timer output pin

10.2.3 Time Constant

Registers B (TCORB)

357

Note added

Note: * When channel 1 and channel 3 are designated for

TCORB input capture, the CMFB flag is not set by a

channel 0 or channel 2 compare match B.

10.2.4 Timer Control

Bits 4 and 3

⎯Counter

Clear 1 and 0 (CCLR1,

CCLR0):

359

Note added

Note: When input capture B is set as the 8TCNT1 and

8TCNT3 counter clear source, 8TCNT0 and 8TCNT2

are not cleared by compare match B.

Bits 2 to 0

⎯Clock

Select 2 to 0 (CSK2 to

CSK0):

Description replaced

10.2.5 Timer

Control/Status Registers

(8TCSR)

Bit 7

⎯Compare

Match/Input Capture

Flag B (CMFB):

362

Note added

Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the

CMFB flag is not set when 8TCNT0 = TCORB0 or

8TCNT2 = TCORB2.

Bit 6

⎯Compare Match

Flag A (CMFA):

Description amended

Status flag that indicates the occurrence of a TCORA compare

match

Bit 4

⎯Reserved (In

8TCSR1):

Bit 4

⎯Input Capture

Enable (ICE) (In

8TCSR1 and 8TCSR3):

363

Description replaced

H8/3006 Datasheet(PDF) 10 Page - Renesas Technology Corp

H8/3006 Datasheet(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL