H8SLASH3006 datasheet(12/796 Pages) RENESAS

12 / 796 page

Rev.5.00 Sep. 12, 2007 Page xii of xxviii

REJ09B0396-0500

Item

Page

Revision (See Manual for Details)

14.3.4 Register

Settings

Smart Card Mode

Settings:

499

Description amended

With the direct convention type, the logic 1 level corresponds to

state Z and the logic 0 level to state A, and transfer is

performed in LSB-first order. In the example above, the first

character data is H'3B. The parity bit is 1, following the even

parity rule designated for smart cards.

14.4 Usage Notes

Note on Block Transfer

Mode Support:

511

Description added

The smart card interface installed in the H8/3006 and H8/3007

support an IC card (smart card) interface with provision for

ISO/IEC7816-3 T=0 (character transmission). Therefore, block

transfer operations are not supported (error signal transmission,

detection, and automatic data retransmission are not

performed).

15.1 Overview

513

Description amended

When the A/D converter is not used, it can be halted

independently to conserve power. For details see section 19.6,

Module Standby Function.

The H8/3006 and H8/3007 support 70/134-state conversion as

a high-speed conversion mode. Note that it differs in this

respect from the H8/3048 Group, which supports 134/266-state

conversion.

15.2.1 A/D Data

Registers A to D

(ADDRA to ADDRD)

517

Description amended

The CPU can always read

the A/D data registers.

536

Table amended

Pin Name

Abbreviation

I/O

Function

16.1.3 Pin

Configuration

Table 16.1 D/A

Converter Pins

Analog power

supply pin

Input

Analog power supply and

reference voltage

Table amended

Item

Symbol

20.2.2 AC

Characteristics

Table 20.7 Control

Signal Timing

581

NMI,

IRQ pulse width

(in recovery from software standby mode)

NMIW

20.3.6 Timer

Input/Output Timing

603

Description amended

The timings of 16-bit and 8-bit timer are shown as follows:

A.3 Number of States

Required for Execution

Table A.4 Number of

Cycles per Instruction

633

Notes amended

Notes: 1. Not available in the H8/3006 and H8/3007.

2. n is the value set in register R4L or R4. The source

and destination are accessed n + 1 times each.

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