H8SLASH3006 datasheet(9/796 Pages) RENESAS

9 / 796 page

Rev.5.00 Sep. 12, 2007 Page ix of xxviii

REJ09B0396-0500

Item

Page

Revision (See Manual for Details)

8.8.2 Register

Configuration

Port B Data Register

(PBDR):

Table 8.16 Port B Pin

Functions

3/TP11/TMIO3/DREQ1/

281

Description amended

The DRAM interface settings by bits DRAS2 to DRAS0 in

DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and

CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB,

and bit PB

3DDR select the pin function as follows.

2/TP10/TMO2/CS5

282

Table amended

Pin Functions and Selection Method

2/TP10/

TMO

2/CS5

The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and

OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB

2DDR

select the pin function as follows.

DRAM interface

settings

(1) in table below

(2) in

table

below

OIS3/2 and

OS1/0

All 0

Not all 0

CS5E

2DDR

NDER10

Pin function

input

output

TMO

output

output*

⎯⎯

⎯

⎯⎯

⎯

⎯⎯

⎯

1/TP9/TMIO1/DREQ0/

Description amended

Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in

8TCR0, bit CS6E in CSCR, bit NDER9 in NDERB, and bit

1DDR select the pin function as follows.

0/TP8/TMO0/CS7

283

Description amended

Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit

NDER8 in NDERB, and bit PB

0DDR select the pin function as

follows.

9.1.4 Register

Configuration

Table 9.3 16-bit timer

Registers

291

Table amended

Channel

Address*

Name

Abbre-

viation

R/W

Initial

Value

Common

H'FFF64

Timer interrupt status register A

TISRA

R/(W)*

H'88

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