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MC33596FCE/R2 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc |
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MC33596FCE/R2 Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 70 page ![]() Register Description MC33596 Data Sheet, Rev. 4 Freescale Semiconductor 37 Values in Table 11 assume the LNA gain is not reduced by the AGC. AFF[1:0] (Average Filter Frequency) define the average filter cut-off frequency if the AFFC bit is set. If AFFC is reset, the average filter frequency is directly defined by bits DR[1:0], as shown in Table 10. If AFFC is set, AFF[1:0] allow the overall receiver sensitivity to be improved by reducing the average filter cut-off frequency. The typical preamble duration of three Manchester zeroes or ones at the data rate must then be increased, as shown in Table 13. 16.2 Command Register Figure 27 describes the Command register, COMMAND. Table 11. RF Input Level Attenuation ILA1 ILA0 RF Input Level Attenuation See Parameter Number 0 0 0 dB 2.5 0 1 8 dB 2.6 1 0 16 dB 2.7 1 1 30 dB 2.8 Table 12. Average Filter Cut-off Frequency AFF1 AFF0 Average Filter Cut-off Frequency 0 0 0.5 kHz 0 1 1 kHz 1 0 2 kHz 1 1 4 kHz Table 13. Minimum Number of Manchester Symbols in Preamble versus DR[1:0] and AFF[1:0] DR[1:0] 00 01 10 11 AFF[1:0] 00 36 12 24 01 —3 6 12 10 —— 3 6 11 ——— 3 |
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