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MC33596FCE/R2 Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc |
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MC33596FCE/R2 Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 70 page ![]() MC33596 Data Sheet, Rev. 4 Receive Mode Freescale Semiconductor 14 Figure 5. Typical Transfer in Receive mode with Data Manager 11.2.1 Data Manager Functions In receive mode, Manchester coded data can be processed internally by the data manager. After decoding, the data is available on the digital interface, in SPI format. This minimizes the load on the MCU. The data manager, when enabled (DME = 1), has five purposes: • First ID detection: the received data are compared with the identifier stored in the ID register. • Then the HEADER recognition: the received data is compared with the data stored in the HEADER register. • Clock recovery: the clock is recovered during reception of the preamble and is computed from the shortest received pulse. While this signal is being received, the recovered clock is constantly updated to the data rate of the incoming signal. • Output data and recovered clock on digital interface: see Figure 5. • End-of-message detection: an EOM consists of two consecutive NRZ ones or zeroes. Table 6 details some MC33596 features versus DME values. 11.2.2 Manchester Coding Description The MC33596 data manager is able to decode Manchester-coded messages. For other codings, the data manager should be disabled (DME=0) for raw data to be available on MOSI. Table 6. the MC33596 Features versus DME DME Digital Interface Use Data Format Output 0 SPI deselected, received data are directly sent to MOSI when CONFB = 1 Bit stream No clock MOSI — 1 SPI master, data sent on MOSI with clock on SCLK when CONFB = 1 Data bytes Recovered clock MOSI SCLK SEB STROBE 1 0 SCLK (Output) MOSI (Output) Recovered Clock Updated to Incoming Signal Data Rate D6 D5 D4 D3 D 2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 CONFB 1 0 D7 D6 D 5 D4 D3 D2 D1 D7 D0 *Refer to (Section 10) SEB STROBE 1 0 SCLK (Output) MOSI (Output) Recovered Clock Updated to Incoming Signal Data Rate D6 D5 D4 D3 D 2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 CONFB 1 0 D7 D6 D 5 D4 D3 D2 D1 D7 D0 *Refer to (Section 10) |
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