MC33596FCESLASHR2 datasheet(56/70 Pages) FREESCALE

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MC33596 Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

19.8 Digital Interface Timing

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 46), unless otherwise specified. Typical values reflect average measurement at VCC =

3.0 V, TA =25°C.

Parameter

Test Conditions

Comments

Limits

Unit

Min

Typ

Max

9.2

SCLK period

—

μs

9.8

Configuration enable time

—

μs

9.3

Enable lead time

Crystal oscillator is running.

3 x Tdigclk

NOTES:

See Section 8.1, “Clock Generator” for Tdigclk values.

——

μs

9.4

Enable lag time

100

—

9.5

Sequential transfer delay

100

—

—2

The digital interface can be used in SPI burst protocol, i.e., with a continuous clock on SCLK port. For example, one (or more)

read access followed by one (or more) write access and so on. In this case and for a practical use, the pulse required on

CONFB between accesses must be higher than 100 ns only if STROBE signal is always set to high level.

9.6

Data hold time

Receive mode, DME = 1,

from SCLK to MOSI

3 x Tdigclk

——

μs

9.7

Data setup time

Configuration mode,

from SCLK to MISO

——

100

9.9

Configuration mode, from

SCLK to MOSI

120

—

9.10 Data setup time

Configuration mode, from

SCLK to MOSI

100

—

MC33596FCE/R2 Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc

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