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MC33596FCE/R2 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc |
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MC33596FCE/R2 Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 70 page  00h CONFIG1-A 91 h 0Dh CONFIG1-B 91 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name LOF1 LOF0 CF1 CF0 RESET SL LVDE CLKE Bit Name LOF1 LOF0 CF1 CF0 — SL LVDE CLKE Reset Value 1 0 0 1 0 0 0 1 Reset Value 1 0 0 1 0 0 0 1 R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R R/W R/WR/W 0 = 304–434 304–315 315–434 314 No T/R No No 0 = 304–434 304–315 315–434 314 — T/R No No 1 = 315–916 434–916 868 434–868 Yes R/T Yes Yes 1 = 315–916 434–916 868 434–868 — R/T Yes Yes 01h CONFIG2-A 10 h 0Eh CONFIG2-B 10 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name DSREF FRM MODU DR1 DR0 TRXE DME SOE Bit Name DSREF FRM MODU DR1 DR0 TRXE DME SOE Reset Value 0 0 0 1 0 0 0 0 Reset Value 0 0 0 1 0 0 0 0 R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR[A] 0 = Fixed Friendly OOK 2.4–4.8 2.4–9.6 Standby No No 0 = Fixed Friendly OOK 2.4–4.8 2.4–9.6 Standby No No 1 = Adaptive Direct FSK 9.6–19.2 4.8–19.2 Enable Yes Yes 1 = Adaptive Direct FSK 9.6–19.2 4.8–19.2 Enable Yes Yes 02h CONFIG3-A 30 h 0Fh CONFIG3-B 30 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name AFF1 AFF0 OLS LVDS ILA1 ILA0 — — Bit Name AFF1 AFF0 OLS LVDS ILA1 ILA0 — — Reset Value 0 0 1 1 0 0 0 0 Reset Value 0 0 1 1 0 0 0 0 R/W R/W R RR R/W R/W R/W R/W R/W R/W R[A] RR[A] R/W R/W R/W R/W 0 = 0.5–1 kHz 0.5–2 kHz RAS RAS 0–8 dB 0–14 dB 0–8 dB 0–14 dB 0 = 0.5–1 kHz 0.5–2 kHz RAS RAS 0–8 dB 0–14 dB 0–8 dB 0–14 dB 1 = 2–4 kHz 1–4 kHz Unlocked Low V 14–24 dB 8–24 dB 14–24 dB 8–24 dB 1 = 2–4 kHz 1–4 kHz Unlocked Low V 14–24 dB 8–24 dB 14–24 dB 8–24 dB 03h COMMAND-A 9 h 10h COMMAND-B 9 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name AFFC IFLA — RSSIE EDD RAGC FAGC BANKS Bit Name AFFC IFLA — RSSIE EDD RAGC FAGC BANKS Reset Value 0 0 0 0 1 0 0 1 Reset Value 0 0 0 0 1 0 0 1 R/WR/W R/WR/W R/WR/W R/WR R/WR/W R/WR/W R/WR/W R/WR[A] 0 = AFFx OFF No RX No Slow dec. No No B Bank 0 = AFFx OFF No RX No Slow dec. No No B Bank 1 = AFFx ON –20 dB TX Yes Fast dec. Yes Yes A Bank 1 = AFFx ON –20 dB TX Yes Fast dec. Yes Yes A Bank 04h F1-A 48 h 11h F1-B 4800 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name FSK3 FSK2 FSK1 FSK0 F11 F10 F9 F8 Bit Name FSK3 FSK2 FSK1 FSK0 F11 F10 F9 F8 Reset Value 0 1 0 0 1 0 0 0 Reset Value 0 1 0 0 1 0 0 0 R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W 05h F2-A 0 h 12h F2-B 0 h Bit 7Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Bit Name F7 F6 F5 F4 F3 F1 F1 F0 Bit Name F7 F6 F5 F4 F3 F1 F1 F0 Reset Value 0 0 0 0 0 0 0 0 Reset Value 0 0 0 0 0 0 0 0 R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W R/WR/W Bank A Registers Bank B Registers Figure 33. Bank Registers |
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