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STM8S105C4B3C Datasheet(PDF) 43 Page - STMicroelectronics |
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STM8S105C4B3C Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 127 page  Reset status Register name Register label Block Address 0x00 TIM2 capture/ compare register 1 low TIM2_CCR1L 0x00 5310 0x00 TIM2 capture/ compare reg. 2 high TIM2_CCR2H 0x00 5311 0x00 TIM2 capture/ compare register 2 low TIM2_CCR2L 0x00 5312 0x00 TIM2 capture/ compare register 3 high TIM2_CCR3H 0x00 5313 0x00 TIM2 capture/ compare register 3 low TIM2_CCR3L 0x00 5314 Reserved area (11 bytes) 0x00 5315 to 0x00 531F 0x00 TIM3 control register 1 TIM3_CR1 TIM3 0x00 5320 0x00 TIM3 interrupt enable register TIM3_IER 0x00 5321 0x00 TIM3 status register 1 TIM3_SR1 0x00 5322 0x00 TIM3 status register 2 TIM3_SR2 0x00 5323 0x00 TIM3 event generation register TIM3_EGR 0x00 5324 0x00 TIM3 capture/ compare mode register 1 TIM3_CCMR1 0x00 5325 0x00 TIM3 capture/ compare mode register 2 TIM3_CCMR2 0x00 5326 43/127 DocID14771 Rev 9 Memory and register map STM8S105xx |
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