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STM8S105C4B3 Datasheet(PDF) 72 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 72 Page - STMicroelectronics |
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72 / 127 page ![]() (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. Total current consumption and timing in forced reset state 10.3.2.6 Table 30: Total current consumption and timing in forced reset state Unit Max (1) Typ Conditions Parameter Symbol μA 500 VDD = 5 V Supply current in reset state (2) IDD(R) 400 VDD = 3.3 V μs 150 Reset pin release to vector fetch tRESETBL (1) Data guaranteed by design, not tested in production. (2) Characterized with all I/Os tied to V SS. Current consumption of on-chip peripherals 10.3.2.7 Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz. Table 31: Peripheral current consumption Unit Typ. Parameter Symbol µA 230 TIM1 supply current (1) IDD(TIM1) 115 TIM2 supply current (1) IDD(TIM2) 90 TIM3 timer supply current (1) IDD(TIM3) 30 TIM4 timer supply current (1) IDD(TIM4) 110 UART2 supply current (2) IDD(UART2) 45 SPI supply current (2) IDD(SPI) DocID14771 Rev 9 72/127 STM8S105xx Electrical characteristics |
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