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STM8S105C4B3 Datasheet(PDF) 35 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 35 Page - STMicroelectronics |
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35 / 127 page  Reset status Register name Register label Block Address 0x18 Clock divider register CLK_CKDIVR 0x00 50C6 0xFF Peripheral clock gating register 1 CLK_PCKENR1 0x00 50C7 0x00 Clock security system register CLK_CSSR 0x00 50C8 0x00 Configurable clock control register CLK_CCOR 0x00 50C9 0xFF Peripheral clock gating register 2 CLK_PCKENR2 0x00 50CA 0x00 CAN clock control register CLK_CANCCR 0x00 50CB xx HSI clock calibration trimming register CLK_HSITRIMR 0x00 50CC x0 SWIM clock control register CLK_SWIMCCR 0x00 50CD Reserved area (3 bytes) 0x00 50CE to 0x00 50D0 0x7F WWDG control register WWDG_CR WWDG 0x00 50D1 0x7F WWDR window register WWDG_WR 0x00 50D2 Reserved area (13 bytes) 0x00 50D3 to 0x00 50DF 35/127 DocID14771 Rev 9 Memory and register map STM8S105xx |
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