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STM8S105C4B3 Datasheet(PDF) 97 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 97 Page - STMicroelectronics |
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97 / 127 page ![]() I 2C interface characteristics 10.3.10 Table 44: I 2C characteristics Unit Fast mode I 2C(1) Standard mode I 2C Parameter Symbol Max (2) Min (2) Max (2) Min (2) μs 1.3 4.7 SCL clock low time tw(SCLL) μs 0.6 4.0 SCL clock high time tw(SCLH) ns 100 250 SDA setup time tsu(SDA) ns 900 (3) 0 (4) 0 (3) SDA data hold time th(SDA) ns 300 1000 SDA and SCL rise time tr(SDA) tr(SCL) ns 300 300 SDA and SCL fall time tf(SDA) tf(SCL) μs 0.6 4.0 START condition hold time th(STA) μs 0.6 4.7 Repeated START condition setup time tsu(STA) μs 0.6 4.0 STOP condition setup time tsu(STO) μs 1.3 4.7 STOP to START condition time (bus free) tw(STO:STA) pF 400 400 Capacitive load for each bus line Cb (1) f MASTER, must be at least 8 MHz to achieve max fast I 2C speed (400kHz). (2) Data based on standard I2C protocol requirement, not tested in production. (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 97/127 DocID14771 Rev 9 Electrical characteristics STM8S105xx |
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