Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

STM8S105C4B3 Datasheet(PDF) 97 Page - STMicroelectronics

Part # STM8S105C4B3
Description  Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
PDF  127 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8S105C4B3 Datasheet(HTML) 97 Page - STMicroelectronics

Back Button STM8S105C4B3 Datasheet HTML 93Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 94Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 95Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 96Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 97Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 98Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 99Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 100Page - STMicroelectronics STM8S105C4B3 Datasheet HTML 101Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 97 / 127 page
background image
I
2C interface characteristics
10.3.10
Table 44: I
2C characteristics
Unit
Fast mode I
2C(1)
Standard mode I
2C
Parameter
Symbol
Max
(2)
Min
(2)
Max
(2)
Min
(2)
μs
1.3
4.7
SCL clock low time
tw(SCLL)
μs
0.6
4.0
SCL clock high time
tw(SCLH)
ns
100
250
SDA setup time
tsu(SDA)
ns
900
(3)
0
(4)
0
(3)
SDA data hold time
th(SDA)
ns
300
1000
SDA and SCL rise time
tr(SDA)
tr(SCL)
ns
300
300
SDA and SCL fall time
tf(SDA)
tf(SCL)
μs
0.6
4.0
START condition hold time
th(STA)
μs
0.6
4.7
Repeated START condition
setup time
tsu(STA)
μs
0.6
4.0
STOP condition setup time
tsu(STO)
μs
1.3
4.7
STOP to START condition time
(bus free)
tw(STO:STA)
pF
400
400
Capacitive load for each bus line
Cb
(1) f
MASTER, must be at least 8 MHz to achieve max fast I
2C speed (400kHz).
(2) Data based on standard I2C protocol requirement, not tested in production.
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time.
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
97/127
DocID14771 Rev 9
Electrical characteristics
STM8S105xx



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com