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STM8S105C4B3 Datasheet(PDF) 99 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 99 Page - STMicroelectronics |
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99 / 127 page ![]() Unit Max Typ Min Conditions Parameter Symbol µs 0.75 fADC = 4 MHz Sampling time tS (2) 0.5 fADC = 6 MHz µs 7 Wakeup time from standby tSTAB µs 3.5 fADC = 4 MHz Total conversion time (including sampling time, 10-bit resolution) tCONV µs 2.33 fADC = 6 MHz 1/fADC 14 (1) Data guaranteed by design, not tested in production.. (2) During the sample time the input capacitance C AIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V Unit Max (1) Typ Conditions Parameter Symbol LSB 2.5 1 fADC = 2 MHz Total unadjusted error (2) |ET| 3 1.4 fADC = 4 MHz 3.5 1.6 fADC = 6 MHz 2 0.6 fADC = 2 MHz Offset error (2) |EO| 2.5 1.1 fADC = 4 MHz 2.5 1.2 fADC = 6 MHz 2 0.2 fADC = 2 MHz Gain error (2) |EG| 2.5 0.6 fADC = 4 MHz 99/127 DocID14771 Rev 9 Electrical characteristics STM8S105xx |
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