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STM8S105C4B3 Datasheet(PDF) 93 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 127 page  Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown inthe following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in the I/O port pin characteristics section. Otherwise the reset is not taken into account internally. Figure 40: Recommended reset pin protection External reset circuit (optional) 0.01 μF NRST VDD RPU Filter Internal reset STM8 SPI serial peripheral interface 10.3.9 Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). 93/127 DocID14771 Rev 9 Electrical characteristics STM8S105xx |
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