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STM8S105C4B3 Datasheet(PDF) 39 Page - STMicroelectronics |
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STM8S105C4B3 Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 127 page  Reset status Register name Register label Block Address 0x00 UART2 guard time register UART2_GTR 0x00 524A 0x00 UART2 prescaler register UART2_PSCR 0x00 524B Reserved area (4 bytes) 0x00 524C to 0x00 524F 0x00 TIM1 control register 1 TIM1_CR1 TIM1 0x00 5250 0x00 TIM1 control register 2 TIM1_CR2 0x00 5251 0x00 TIM1 slave mode control register TIM1_SMCR 0x00 5252 0x00 TIM1 external trigger register TIM1_ETR 0x00 5253 0x00 TIM1 interrupt enable register TIM1_IER 0x00 5254 0x00 TIM1 status register 1 TIM1_SR1 0x00 5255 0x00 TIM1 status register 2 TIM1_SR2 0x00 5256 0x00 TIM1 event generation register TIM1_EGR 0x00 5257 0x00 TIM1 capture/ compare mode register 1 TIM1_CCMR1 0x00 5258 0x00 TIM1 capture/compare mode register 2 TIM1_CCMR2 0x00 5259 39/127 DocID14771 Rev 9 Memory and register map STM8S105xx |
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