MC9S08DN60F1CLF datasheet(147/356 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

147

— If entering FEE, set RDIV appropriately, clear the IREFS bit to switch to the external reference,

and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock

source.

— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS

bits to %10 so that the external reference clock is selected as the system clock source. The

RDIV bits should also be set appropriately here according to the external reference frequency

because although the FLL is bypassed, it is still on in FBE mode.

— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is

useful if the application will switch back and forth between internal and external modes. For

minimum power consumption, leave the internal reference disabled while in an external clock

mode.

3. After the proper conﬁguration bits have been set, wait for the affected bits in the MCGSC register

to be changed appropriately, reﬂecting that the MCG has moved into the proper mode.

— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and

EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the

external clock source has ﬁnished its initialization cycles and stabilized. Typical crystal startup

times are given in Appendix A, “Electrical Characteristics”.

— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before

moving on.

— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the

CLKST bits have changed to %10 indicating the external reference clock has been

appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock

in FBE mode.

To change from FEI clock mode to FBI clock mode, follow this procedure:

1. Change the CLKS bits to %01 so that the internal reference clock is selected as the system clock

source.

2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal

reference clock has been appropriately selected.

8.5.2

MCG Mode Switching

When switching between operational modes of the MCG, certain conﬁguration bits must be changed in

order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,

CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or

OSCINIT) must be checked before moving on in the application software.

Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the

mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001

(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required

frequency between 1 and 2 MHz.

The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or

PLL clock has an appropriate reference clock frequency to switch to.

MC9S08DN60F1CLF Datasheet(PDF) 147 Page - Freescale Semiconductor, Inc

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