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MC9S08DN60F1CLF Datasheet(PDF) 154 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 154 Page - Freescale Semiconductor, Inc |
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154 / 356 page ![]() Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 154 Freescale Semiconductor Figure 8-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz crystal 8.5.2.4 Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE mode until the 8 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. This example is similar to example number one except that in this case the frequency of the external crystal is 8 MHz instead of 4 MHz. Special consideration must be taken with this case since there is a period of time along the way from FEI mode to PEE mode where the FLL operates based on a reference clock with a frequency that is greater than the maximum allowed for the FLL. This occurs because with an 8 MHz MCGC2 = $36 CHECK OSCINIT = 1 ? MCGC1 = $38 CHECK IREFST = 0? CHECK CLKST = %00? CONTINUE IN FEE MODE START IN BLPI MODE YES YES NO NO NO MCGC2 = $00 OPTIONAL: CHECK LOCK = 1? YES NO YES OPTIONAL: CHECK LOCK = 1? YES NO |
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