68HC05CL48 datasheet(111/145 Pages) MOTOROLA

111 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

INSTRUCTION SET

MOTOROLA

REV 2.0

14-1

SECTION 14

INSTRUCTION SET

This section describes the addressing modes and instruction types.

14.1

ADDRESSING MODES

The CPU uses eight addressing modes for ﬂexibility in accessing data. The

addressing modes deﬁne the manner in which the CPU ﬁnds the data required to

execute an instruction. The eight addressing modes are the following:

•

Inherent

•

Immediate

•

Direct

•

Extended

•

Indexed, No Offset

•

Indexed, 8-Bit Offset

•

Indexed, 16-Bit Offset

•

Relative

14.1.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt

(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU

registers, such as set carry ﬂag (SEC) and increment accumulator (INCA). Inher-

ent instructions require no memory address and are one byte long.

14.1.2 Immediate

Immediate instructions are those that contain a value to be used in an operation

with the value in the accumulator or index register. Immediate instructions require

no memory address and are two bytes long. The opcode is the ﬁrst byte, and the

immediate data value is the second byte.

14.1.3 Direct

Direct instructions can access any of the ﬁrst 256 memory addresses with two

bytes. The ﬁrst byte is the opcode, and the second is the low byte of the operand

address. In direct addressing, the CPU automatically uses $00 as the high byte of

the operand address. BRSET and BRCLR are three-byte instructions that use

direct addressing to access the operand and relative addressing to specify a

branch destination.

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