68HC05P9A datasheet(30/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

INTERRUPTS

MC68HC05P9A

4-4

Rev. 2.0

4.3

External Interrupt

The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector ﬂip-

ﬂop is latched on the falling edge of IRQ. If either the output from the internal edge

detector ﬂip-ﬂops or the level on the IRQ pin is low, a request is synchronized to

the CPU to generate the IRQ interrupt. If the edge-sensitive only mask 0ption is

selected, the output of the internal edge detector ﬂip-ﬂop is sampled and the input

level on the IRQ pin is ignored. The interrupt service routine address is speciﬁed

by the contents of memory locations $1FFA and $1FFB. A block diagram of the

IRQ function is shown in Figure 4-2.

NOTE

The internal interrupt latch is cleared nine PH2 clock cycles after the

interrupt is recognized (after location $1FFA is read). Therefore,

another external interrupt pulse can be latched during the IRQ

service routine.

NOTE

When the edge- and level-sensitive mask option is selected, the

voltage applied to the IRQ pin must return to the high state before

the RTI instruction in the interrupt service routine is executed to

avoid the processor re-entering the IRQ service routine.

Figure 4-2. IRQ Function Block Diagram

IRQ

LATCH

VDD

IRQ PIN

MASK OPTION

(IRQ LEVEL)

TO IRQ

PROCESSING

IN CPU

TO BIH & BIL

INSTRUCTION

SENSING

RST

IRQ VECTOR FETCH

PA7

DDRA7

PA0

DDRA0

PA0 IRQ INHIBIT

(MASK OPTION)

PA7 IRQ INHIBIT

(MASK OPTION)

Freescale Semiconductor, Inc.

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68HC05P9A Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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