68HC05P9A datasheet(17/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

GENERAL DESCRIPTION

Rev. 2.0

1-7

1.6

Input/Output Programming

Port pins may be programmed as inputs or outputs under software control. The

direction of the pins is determined by the state of the corresponding bit in the port

data direction register (DDR). Each I/O port has an associated DDR. Any I/O

port pin is conﬁgured as an output if its corresponding DDR bit is set to a logic

one. A pin is conﬁgured as an input if its corresponding DDR bit is cleared to a

logic zero.

At power-on or reset, all DDRs are cleared, which conﬁgures all pins as inputs.

The data direction registers are capable of being written to or read by the

processor. During the programmed output state, a read of the data register

actually reads the value of the output data latch and not the I/O pin. For further

information, see Table 1-1 and Figure 1-4.

Figure 1-4. I/O Circuitry

Table 1-1. I/O Pin Functions

R/W

DDR

I/O Pin Function

The I/O pin is in input mode. Data is written into the output data latch.

Data is written into the output data latch and output to the I/O pin.

The state of the I/O pin is read.

The I/O pin is in an output mode. The output data latch is read.

R/W is an internal signal.

Data Direction

Latched Output

Data Bit

I/O

Input

Reg

Bit

Input

I/O

Output

Internal

HC05

Connections

Freescale Semiconductor, Inc.

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68HC05P9A Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

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