68HC05P9A datasheet(36/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

LOW POWER MODES

MC68HC05P9A

6-2

Rev. 2.0

6.1.2 Halt Mode

Execution of the STOP instruction with the conversion to halt places the MCU in

this low-power mode. Halt mode consumes the same amount of power as wait

mode. (Both halt and wait modes consume more power than stop mode.)

In halt mode the PH2 clock is halted, suspending all processor and internal bus

activity. Internal timer clocks remain active, permitting interrupts to be generated

from the 16-bit timer or a reset to be generated from the COP watchdog timer.

Execution of the STOP instruction automatically clears the I bit in the condition

code register enabling the IRQ external interrupt. All other registers, memory, and

input/output lines remain in their previous states.

If the 16-bit timer interrupt is enabled, the processor will exit the halt mode and

resume normal operation. The halt mode can also be exited when an IRQ external

interrupt or external RESET occurs. When exiting the halt mode, the PH2 clock

will resume after a delay of one to 4064 PH2 clock cycles. This varied delay time

is the result of the halt mode exit circuitry testing the oscillator stabilization delay

timer (a feature of the stop mode), which has been free-running (a feature of the

wait mode).

NOTE

The halt mode is not intended for normal use. This feature is

provided to keep the COP watchdog timer active in the event a

STOP instruction is inadvertently executed.

6.2

WAIT Instruction

The WAIT instruction places the MCU in a low-power mode, which consumes

more power than the stop mode. In wait mode, the PH2 clock is halted,

suspending all processor and internal bus activity. Internal timer clocks remain

active, permitting interrupts to be generated from the 16-bit timer and reset to be

generated from the COP watchdog timer. Execution of the WAIT instruction

automatically clears the I bit in the condition code register enabling the IRQ

external interrupt. All other registers, memory, and input/output lines remain in

their previous state.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit the wait

mode and resume normal operation. The 16-bit timer may be used to generate a

periodic exit from the wait mode. The wait mode may also be exited when an IRQ

external interrupt or RESET occurs.

Freescale Semiconductor, Inc.

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