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PCIMX536AVV8B Datasheet(PDF) 103 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B Datasheet(HTML) 103 Page - Freescale Semiconductor, Inc |
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103 / 180 page  Electrical Characteristics i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 103 IP39 Setup time for wait signal Tswait — — — — IP47 Read time point Tdrp Tdrp – 1.24 Tdrp Tdrp+1.24 ns 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2Display period value for read ACCESS_SIZE is predefined in REGISTER. 3Display period value for write ACCESS_SIZE is predefined in REGISTER. 4Display control down for CS DISP_DOWN is predefined in REGISTER. 5Display control up for CS DISP_UP is predefined in REGISTER. 6Display control down for RS DISP_DOWN is predefined in REGISTER. 7Display control up for RS DISP_UP is predefined in REGISTER. 8Display control down for read DISP_DOWN is predefined in REGISTER. Table 61. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued) ID Parameter Symbol Min Typ1 Max Unit Tdicpr T DI_CLK ceil × DI_ACCESS_SIZE_# DI_CLK_PERIOD ----------------------------------------------------- = Tdicpw T DI_CLK ceil × DI_ACCESS_SIZE_# DI_CLK_PERIOD ----------------------------------------------------- = Tdicdcs 1 2 ---T DI_CLK ceil × 2 DISP_DOWN_# × DI_CLK_PERIOD -------------------------------------------------- ⎝⎠ ⎛⎞ = Tdicucs 1 2 ---T DI_CLK ceil × 2 DISP_UP_# × DI_CLK_PERIOD ---------------------------------------------- ⎝⎠ ⎛⎞ = Tdicdrs 1 2 ---T DI_CLK ceil × 2 DISP_DOWN_# × DI_CLK_PERIOD -------------------------------------------------- ⎝⎠ ⎛⎞ = Tdicurs 1 2 ---T DI_CLK ceil × 2DISP_UP_# × DI_CLK_PERIOD ---------------------------------------------- ⎝⎠ ⎛⎞ = Tdicdr 1 2 ---T DI_CLK ceil × 2 DISP_DOWN_# × DI_CLK_PERIOD -------------------------------------------------- ⎝⎠ ⎛⎞ = |
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