PCIMX536AVV8B datasheet(124/180 Pages) FREESCALE

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i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

124

Freescale Semiconductor

Electrical Characteristics

4.7.14

SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.7.14.1

Reference Clock Electrical and Jitter Specifications

The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and

125 MHz are common frequencies). The frequency is pin-selectable (for more information about the

signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference

Manual).

Table 76 provides the SATA PHY reference clock specifications.

trfs1

trfs

trfs = 1.6

× T + tsui + tco + tbuf + tbuf

—

tdzfs

tdzfs = time_dzfs

× T – (tskew1)

time_dzfs

tss

tss = time_ss

× T – (tskew1 + tskew2)

time_ss

tmli

tdzfs_mli

tdzfs_mli =max (time_dzfs, time_mli)

× T – (tskew1 + tskew2)

—

tli

tli1

tli1 > 0

—

tli

tli2

tli2 > 0

—

tli

tli3

tli3 > 0

—

tcvh

tcvh = (time_cvh

×T) – (tskew1 + tskew2)

time_cvh

—ton

toff

ton = time_on

× T – tskew1

toff = time_off

× T – tskew1

—

Table 76. Reference Clock Specifications

Parameters

Test Conditions

Min

Max

Unit

Differential peak voltage (typically 0.71 V)

—

350

850

Common mode voltage

(refclk_p + refclk_m) / 2

—

175

2,000

Total phase jitter

For information about total

phase jitter, see following

section

—3

ps RMS

Minimum/maximum duty cycle

—

% UI

Frequency range

—

156.25

MHz

Table 75. UDMA Out Burst Timing Parameters (continued)

ATA

Parameter

from

Figure 75,

Figure 76,

Figure 77

Value

Controlling

Variable

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