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PCIMX536AVV8B Datasheet(PDF) 127 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B Datasheet(HTML) 127 Page - Freescale Semiconductor, Inc |
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127 / 180 page  Electrical Characteristics i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 127 4.7.15 SCAN JTAG Controller (SJC) Timing Parameters Figure 79 depicts the SJC test clock input timing. Figure 80 depicts the SJC boundary scan timing. Figure 81 depicts the SJC test access port. Signal parameters are listed in Table 79. Figure 79. Test Clock Input Timing Diagram Figure 80. Boundary Scan (JTAG) Timing Diagram TCK (Input) VM VM VIH VIL SJ1 SJ2 SJ2 SJ3 SJ3 TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid Output Data Valid SJ4 SJ5 SJ6 SJ7 SJ6 |
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