PIC16F1526 datasheet(197/354 Pages) MICROCHIP

197 / 354 page

 2011 Microchip Technology Inc.

Preliminary

DS41458A-page 197

PIC16(L)F1526/27

20.4

CCP Control Registers

CCPxCON: CCPx CONTROL REGISTER

U-0

R/W-0/0

—

DCxB<1:0>

CCPxM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-6

Unimplemented:

Read as ‘0’

bit 5-4

DCxB<1:0>:

PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0

CCPxM<3:0>:

CCPx Mode Select bits

0000

= Capture/Compare/PWM off (resets CCPx module)

0001

= Reserved

0010

= Compare mode: toggle output on match

0011

= Reserved

0100

= Capture mode: every falling edge

0101

= Capture mode: every rising edge

0110

= Capture mode: every 4th rising edge

0111

= Capture mode: every 16th rising edge

1000

= Compare mode: set output on compare match (set CCPxIF)

1001

= Compare mode: clear output on compare match (set CCPxIF)

1010

= Compare mode: generate software interrupt only

1011

= Compare mode: Special Event Trigger (sets CCP10IF bit (CCP10), starts A/D conversion if A/D module

is enabled)(1)

11xx

=PWM mode

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