R5F110ME datasheet(47/153 Pages) RENESAS

47 / 153 page

RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 47 of 149

Feb 21, 2014

Note 1.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 2.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 3.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from

SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 4.

C is the load capacitance of the SOp output lines.

Note 5.

The maximum transfer rate when using the SNOOZE mode is 1 Mbps.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input

mode register g (PIMg) and port output mode register g (POMg).

Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),

g: PIM number (g = 0 to 3)

Remark 2.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13))

(4)

During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(TA = -40 to +85 °C, 1.6 V  VDD  3.6 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

LS (low-speed main)

Mode

LV (low-voltage main)

Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle

time Note 5

tKCY2

2.7 V

 VDD  3.6 V

fMCK

 16 MHz

8/fMCK

——

fMCK

 16 MHz

6/fMCK

2.4 V

 VDD  3.6 V

6/fMCK

and 500

6/fMCK

and 500

6/fMCK

and 500

1.8 V

 VDD  3.6 V

—

6/fMCK

and 750

6/fMCK

and 750

1.6 V

 VDD  3.6 V

—

6/fMCK

and 1500

SCKp high-/

low-level width

tKH2, tKL2

2.7 V

 VDD  3.6 V

tKCY2/2 - 8

1.8 V

 VDD  3.6 V

—

tKCY2/2 - 18

1.6 V

 VDD  3.6 V

—

tKCY1/2 - 66

SIp setup time

(to SCKp

↑)

Note 1

tSIK2

2.7 V

 VDD  3.6 V

1/fMCK + 20

1/fMCK + 30

2.4 V

 VDD  3.6 V

1/fMCK + 30

1.8 V

 VDD  3.6 V

—

1/fMCK + 30

1.6 V

 VDD  3.6 V

—

1/fMCK + 40

SIp hold time

(from SCKp

↑)

Note 2

tKSI2

2.4 V

 VDD  3.6 V

1/fMCK + 31

1.8 V

 VDD  3.6 V

—

1/fMCK + 31

1.6 V

 VDD  3.6 V

—

1/fMCK + 250

Delay time

from SCKp

↓ to

SOp output

Note 3

tKSO2

C = 30 pF Note 4

2.7 V

 VDD  3.6 V

2/fMCK

+ 44

2/fMCK

+ 110

2/fMCK

+ 110

2.4 V

 VDD  3.6 V

2/fMCK

+ 75

2/fMCK

+ 110

2/fMCK

+ 110

1.8 V

 VDD  3.6 V

—

2/fMCK

+ 110

2/fMCK

+ 110

1.6 V

 VDD  3.6 V

—

2/fMCK

+ 220

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