R5F110ME datasheet(78/153 Pages) RENESAS

78 / 153 page

RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 78 of 149

Feb 21, 2014

2.6.4

Comparator

Note

Not usable in LS (low-speed main) mode, LV (low-voltage main) mode, sub-clock operation, or STOP mode.

2.6.5

POR circuit characteristics

Note

Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a

POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main

system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register

(CSC).

(TA = -40 to +85 °C, 1.6 V  VDD  3.6 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage range

Ivref

VDD - 1.4

Ivcmp

-0.3

VDD + 0.3

Output delay

VDD = 3.0 V

Input slew rate > 50 mV/

s

High-speed comparator mode,

standard mode

1.2

s

High-speed comparator mode,

window mode

2.0

s

Low-speed comparator mode,

standard mode

35.0

s

High-electric-potential

judgment voltage

VTW+

High-speed comparator mode, window mode

0.76 VDD

Low-electric-potential

judgment voltage

VTW-

High-speed comparator mode, window mode

0.24 VDD

Operation stabilization

wait time

tCMP

100

s

Internal reference

voltage Note

VBGR

1.38

1.45

1.50

(TA = -40 to +85 °C, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Detection voltage

VPOR

Power supply rise time

1.47

1.51

1.55

VPDR

Power supply fall time Note

1.46

1.50

1.54

Minimum pulse width

TPW

300

s

TPW

VPOR

VPDR or 0.7 V

Supply voltage (VDD)

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