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UPSD3312D Datasheet(PDF) 62 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 62 Page - STMicroelectronics |
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62 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Interrupt system UPSD33xx 62/272 Doc ID 9685 Rev 7 interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes from the stack and loads them into the PC. Execution of the interrupted program continues where it left off. Note: An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt control system that the ISR is complete, leaving the MCU to think the ISR is still in progress, making future interrupts impossible. Table 18. Interrupt summary Interrupt source Polling priority Vector addr. Flag bit name (SFR.bit position) 1 = Intr pending 0 = No interrupt Flag bit auto- cleared by hardware Enable bit name (SFR.bit position) 1 = Intr enabled 0 = Intr disabled Priority bit name (SFR.bit position) 1= high priority 0 = low priority Reserved 0 (high) 0063h – – – – External Interrupt INT0 1 0003h IE0 (TCON.1) Edge - Yes Level - No EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 2 000Bh TF0 (TCON.5) Yes ET0 (IE.1) PT0 (IP.1) External Interrupt INT1 3 0013h IE1 (TCON.3 Edge - Yes Level - No EX1 (IE.2) PX1 (IP.2) Timer 1 Overflow 4 001Bh TF1 (TCON.7) Yes ET1 (IE.3) PT1 (IP.3) UART0 5 0023h RI (SCON0.0) TI (SCON0.1) No ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow or TX2 Pin 6 002Bh TF2 (T2CON.7) EXF2 (T2CON.6) No ET2 (IE.5) PT2 (IP.5) SPI 7 0053h TEISF, RORISF, TISF, RISF (SPISTAT[3:0]) Yes ESPI (IEA.6) PSPI (IPA.6) Reserved 8 0033h – – – – I2C 9 0043h INTR (S1STA.5) Yes EI2C (IEA.1) PI2C (IPA.1) ADC 10 003Bh AINTF (ACON.7) No EADC (IEA.7) PADC (IPA.7) PCA 11 005Bh OFVx, INTFx (PCASTA[0:7]) No EPCA (IEA.5) PPCA (IPA.5) UART1 12 (low) 004Bh RI (SCON1.0) TI (SCON1.1) No ES1 (IEA.4) PS1 (IPA.4) |
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