UPSD3312D datasheet(72/272 Pages) STMICROELECTRONICS

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UPSD33xx

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Doc ID 9685 Rev 7

Table 29.

MCU module port and peripheral status during reduced power modes

Table 30.

State of 8032 MCU bus Signals during Power-down and Idle modes

Table 31.

PCON: Power Control register (SFR 87h, reset value 00h)

Mode

Ports 1,

3, 4

PCA

SPI

I2C

ADC

SUPER

VISOR

UART0,

UART1

TIMER

0,1,2

EXT

INT0, 1

Idle

Maintain

Data

Active

Active(1)

The watchdog timer is not active during Idle mode. Other supervisor functions are active: LVD, external

reset, JTAG debug reset

Active

Powe

down

Maintain

Data

Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled

Mode

ALE

PSEN_

RD_

WR_

AD0-7

A8-15

Idle

0111

FFh

Power-down

0111

FFh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMOD0

SMOD1

–

POR

RCLK1

TCLK1

IDL

Table 32.

PCON register bit definition

Bit

Symbol

R/W

Function

7SMOD0

R,W

Baud Rate Double Bit (UART0)

0 = No Doubling

1 = Doubling

(See Section 21.3: UART baud rates on

page 110 for details.)

6SMOD1

R,W

Baud Rate Double Bit for 2nd UART

(UART1)

0 = No Doubling

1 = Doubling

(See Section 21.3: UART baud rates on

page 110 for details.)

–

Reserved

4POR

R,W

Only a power-on, and a Reset sets this bit

(cold reset). Warm reset will not set this bit.

'0,' Cleared to zero with firmware

'1,' Is set only by a power-on reset generated

by Supervisory circuit (see Section 19.3:

Power-up reset on page 90 for details).

RCLK1

R,W

Received Clock Flag (UART1)

(See Table 58 on page 100 for flag

description.)

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