UPSD3312D datasheet(34/272 Pages) STMICROELECTRONICS

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8032 MCU core performance enhancements

UPSD33xx

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Doc ID 9685 Rev 7

transparent and a full 10 MIPS is achieved when the program stream consists of sequential

one-byte, one machine-cycle instructions as shown in Figure 6 on page 32 (transparent

because a machine-cycle is four MCU clocks which equals the memory pre-fetch wait time

that is also four MCU clocks). But it is also important to understand PFQ operation on multi-

cycle instructions.

5.2

PFQ example, multi-cycle instructions

Let us look at a string of two-byte, two-cycle instructions in Figure 8. There are three

instructions executed sequentially in this example, instructions A, B, and C. Each of the time

divisions in the figure is one machine-cycle of four clocks, and there are six phases to

reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of

execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes

(A1 and A2) of instruction A. During Phase one, both bytes are loaded into the MCU

execution unit. Also in Phase 1, the PFQ is pre-fetching the first byte (B1) of instruction B

from program memory. In Phase 2, the MCU is processing instruction A internally while the

PFQ is pre-fetching the second byte (B2) of instruction B. In Phase 3, both bytes of

instruction B are loaded into the MCU execution unit and the PFQ begins to pre-fetch bytes

for the third instruction C. In Phase 4 instruction B is processed and the pre-fetching

continues, eliminating idle bus cycles and feeding a continuous flow of operands and

opcodes to the MCU execution unit.

The UPSD33xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions

with regard to number of cycles per instruction. Figure 9 on page 35 shows the equivalent

instruction sequence from the example above on a standard 8032 for comparison.

5.3

Aggregate performance

The stream of two-byte, two-cycle instructions in Figure 8, running on a 40 MHz, 5 V,

UPSD33xx will yield 5 MIPs. And we saw the stream of one-byte, one-cycle instructions in

Figure 6 on page 32, on the same MCU yield 10 MIPs. Effective performance will depend on

a number of things: the MCU clock frequency; the mixture of instructions types (bytes and

cycles) in the application; the amount of time an empty PFQ stalls the MCU (mix of

instruction types and misses on Branch Cache); and the operating voltage. A 5 V

UPSD33xx device operates with four memory wait states, but a 3.3 V device operates with

five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5 V device.

The same number of wait states will apply to both program fetches and to data

READ/WRITEs unless otherwise specified in the SFR named BUSCON.

In general, a 3X aggregate performance increase is expected over any standard 8032

application running at the same clock frequency.

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