UPSD3312D datasheet(32/272 Pages) STMICROELECTRONICS

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8032 MCU core performance enhancements

UPSD33xx

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Doc ID 9685 Rev 7

8032 MCU core performance enhancements

Before describing performance features of the UPSD33xx, let us first look at standard 8032

architecture. The clock source for the 8032 MCU creates a basic unit of timing called a

machine-cycle, which is a period of 12 clocks for standard 8032 MCUs. The instruction set

for traditional 8032 MCUs consists of 1, 2, and 3 byte instructions that execute in different

combinations of 1, 2, or 4 machine-cycles. For example, there are one-byte instructions that

execute in one machine-cycle (12 clocks), one-byte instructions that execute in four

machine-cycles (48 clocks), two-byte, two-cycle instructions (24 clocks), and so on. In

addition, standard 8032 architecture will fetch two bytes from program memory on almost

every machine-cycle, regardless if it needs them or not (dummy fetch). This means for one-

byte, one-cycle instructions, the second byte is ignored. These one-byte, one-cycle

instructions account for half of the 8032's instructions (126 out of 255 opcodes). There are

inefficiencies due to wasted bus cycles and idle bus times that can be eliminated.

The UPSD33xx 8032 MCU core offers increased performance in a number of ways, while

keeping the exact same instruction set as the standard 8032 (all opcodes, the number of

bytes per instruction, and the native number a machine-cycles per instruction are identical to

the original 8032). The first way performance is boosted is by reducing the machine-cycle

period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032. This

shortened machine-cycle improves the instruction rate for one-byte, one-cycle instructions

by a factor of three (Figure 6) compared to standard 8051 architectures, and significantly

improves performance of multiple-cycle instruction types.

The example in Figure 6 shows a continuous execution stream of one-byte, one-cycle

instructions. The 5 V UPSD33xx will yield 10 MIPS peak performance in this case while

operating at 40 MHz clock rate. In a typical application however, the effective performance

will be lower since programs do not use only one-cycle instructions, but special techniques

are implemented in the UPSD33xx to keep the effective MIPS rate as close as possible to

the peak MIPS rate at all times. This is accomplished with an instruction Pre-Fetch Queue

(PFQ) and a Branch Cache (BC) as shown in Figure 7 on page 33.

Figure 6.

Comparison of UPSD33xx with standard 8032 performance

MCU Clock

Standard 8032

Fetch Byte for Instruction A

Execute Instruction A

and Fetch a Second Dummy Byte

Turbo UPSD33XX

Execute Instruction and

Pre-Fetch Next Instruction

4 clocks (one machine cycle)

12 clocks (one machine cycle)

1-byte, 1-Cycle Instructions

Dummy Byte is Ignored (wasted bus access)

Execute Instruction and

Pre-Fetch Next Instruction

Execute Instruction and

Pre-Fetch Next Instruction

Instruction A

Instruction B

Instruction C

Instruction A

Turbo UPSD33XX executes instructions A, B, and C in the same

amount of time that a standard 8032 executes only instruction A.

one machine cycle

AI08808b

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