UPSD3312D datasheet(90/272 Pages) STMICROELECTRONICS

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Supervisory functions

UPSD33xx

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Doc ID 9685 Rev 7

19.2

Low VCC voltage detect, LVD

An internal reset is generated by the LVD circuit when VCC drops below the reset threshold,

VLV_THRESH. After VCC returns to the reset threshold, the MCU_RESET signal will remain

asserted for tRST_ACTV before it is released. The LVD circuit is always enabled (cannot be

disabled by SFR), even in Idle mode and Power-down mode. The LVD input has a voltage

hysteresis of VRST_HYS and will reject voltage spikes less than a duration of tRST_FIL.

Note:

Important: The LVD voltage threshold is VLV_THRESH, suitable for monitoring both the 3.3 V

VCC supply on the MCU module and the 3.3 V VDD supply on the PSD module for 3.3 V

UPSD33xxV devices, since these supplies are one in the same on the circuit board.

However, for 5 V UPSD33xx devices, VLV_THRESH is not suitable for monitoring the 5 V VDD

voltage supply (VLV_THRESH is too low), but good for monitoring the 3.3 V VCC supply. In the

case of 5 V UPSD33xx devices, an external means is required to monitor the separate 5 V

VDD supply, if desired.

19.3

Power-up reset

At power up, the internal reset generated by the LVD circuit is latched as a logic '1' in the

POR bit of the SFR named PCON (Table 31 on page 72). Software can read this bit to

determine whether the last MCU reset was the result of a power up (cold reset) or a reset

from some other condition (warm reset). This bit must be cleared with software.

19.4

JTAG debug Reset

The JTAG debug unit can generate a reset for debugging purposes. This reset source is

also available when the MCU is in Idle mode and Power-down mode (the JTAG debugger

can be used to exit these modes).

19.5

Watchdog timer (WDT)

When enabled, the WDT will generate a reset whenever it overflows. Firmware that is

behaving correctly will periodically clear the WDT before it overflows. Run-away firmware

will not be able to clear the WDT, and a reset will be generated.

By default, the WDT is disabled after each reset.

Note:

The WDT is not active during Idle mode or Power-down mode.

There are two SFRs that control the WDT, they are WDKEY (Table 50 on page 92) and

WDRST (Table 52 on page 92).

If WDKEY contains 55h, the WDT is disabled. Any value other than 55h in WDKEY will

enable the WDT. By default, after any reset condition, WDKEY is automatically loaded with

55h, disabling the WDT. It is the responsibility of initialization firmware to write some value

other than 55h to WDKEY after each reset if the WDT is to be used.

The WDT consists of a 24-bit up-counter (Figure 20), whose initial count is 000000h by

default after every reset. The most significant byte of this counter is controlled by the SFR,

WDRST. After being enabled by WDKEY, the 24-bit count is increased by 1 for each MCU

machine cycle. When the count overflows beyond FFFFFh (224 MCU machine cycles), a

reset is issued and the WDT is automatically disabled (WDKEY = 55h again).

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