UPSD3312D datasheet(85/272 Pages) STMICROELECTRONICS

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MCU bus interface

Doc ID 9685 Rev 7

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MCU bus interface

The MCU module has a programmable bus interface. It is based on a standard 8032 bus,

with eight data signals multiplexed with eight low-order address signals (AD[7:0]). It also has

eight high-order non-multiplexed address signals (A[15:8]). Time multiplexing is controlled

by the address latch signal, ALE.

This bus connects the MCU module to the PSD module, and also connects to external pins

only on 80-pin devices. See the Section 28: AC/DC parameters on page 242 at the end of

this document for external bus timing on 80-pin devices.

Four types of data transfers are supported, each transfer is to/from a memory location

external to the MCU module:

●

Code Fetch cycle using the PSEN signal: fetch a code byte for execution

●

Code Read cycle using PSEN: read a code byte using the MOVC (Move Constant)

instruction

●

XDATA Read cycle using the RD signal: read a data byte using the MOVX (Move

eXternal) instruction

●

XDATA Write cycle using the WR signal: write a data byte using the MOVX instruction

The number of MCU_CLK periods for these transfer types can be specified at runtime by

firmware writing to the SFR register named BUSCON (Table 47 on page 87). Here, the

number of MCU_CLK clock pulses per bus cycle are specified to maximize performance.

Note:

Important: By default, the BUSCON register is loaded with long bus cycle times (6

MCU_CLK periods) after a reset condition. It is important that the post-reset initialization

firmware sets the bus cycle times appropriately to get the most performance, according to

Table 49 on page 88. Keep in mind that the PSD module has a faster Turbo mode (default)

and a slower but less power consuming Non-Turbo mode. The bus cycle times must be

programmed in BUSCON to optimize for each mode as shown in Table 49 on page 88. See

Section 27.4.55: PLD non-turbo mode on page 230 for more details.

18.1

Bus read cycles (PSEN or RD)

When the PSEN signal is used to fetch a byte of code, the byte is read from the PSD module

or external device and it enters the MCU Pre-Fetch Queue (PFQ). When PSEN is used

during a MOVC instruction, or when the RD signal is used to read a byte of data, the byte is

routed directly to the MCU, bypassing the PFQ.

Bits in the BUSCON register determine the number of MCU_CLK periods per bus cycle for

each of these kinds of transfers to all address ranges.

It is not possible to specify in the BUSCON register a different number of MCU_CLK periods

for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for

RD read cycles to one address range on the PSD module, and 5 MCU_CLK periods for RD

read cycles to a different address range on an external device. However, the user can

specify one number of clock periods for PSEN read cycles and a different number of clock

periods for RD read cycles.

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