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UPSD3312D Datasheet(PDF) 101 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 101 Page - STMicroelectronics |
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101 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx Standard 8032 timer/counters Doc ID 9685 Rev 7 101/272 Table 60. Timer/counter 2 operating modes 1C/T2 R,W Counter or Timer function select. When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 = 1, function is counter, clocked by signal sampled on external pin, T2. 0CP/RL2 R,W Capture/Reload. When CP/RL2 = 1, capture occurs on negative transition at pin T2X if EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2 overflows, or on negative transition at pin T2X when EXEN2=1. When RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to auto-reload upon Timer 2 overflow 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK. Mode Bits in T2CON SFR Pin T2X (1) 1. ↓ = falling edge Remarks Input clock RCLK or TCLK CP/RL2 TR2 EXEN2 Timer, internal Counter, external (pin T2, P1.0) 16-bit Auto- reload 00 1 0 x reload [RCAP2H, RCAP2L] to [TH2, TL2] upon overflow (up counting) fOSC/12 MAX fOSC/24 00 1 1 ↓ reload [RCAP2H, RCAP2L] to [TH2, TL2] at falling edge on pin T2X 16-bit Capture 01 1 0 x 16-bit Timer/Counter (up counting) fOSC/12 MAX fOSC/24 01 1 1 ↓ Capture [TH2, TL2] and store to [RCAP2H, RCAP2L] at falling edge on pin T2X Baud Rate Generator 1x 1 0 x No overflow interrupt request (TF2) fOSC/2 – 1x 1 1 ↓ Extra Interrupt on pin T2X, sets TF2 Off x x 0 x x Timer 2 stops – – Table 59. T2CON register bit definition Bit Symbol R/W Definition |
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