UPSD3312DV datasheet(96/272 Pages) STMICROELECTRONICS

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Standard 8032 timer/counters

UPSD33xx

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Doc ID 9685 Rev 7

20.3

SFR, TCON

Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides

information about them. See Table 54 on page 95.

Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware

when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For

system information on all of these interrupts, see Table 18 on page 62, Interrupt Summary.

Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not

the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered.

20.4

SFR, TMOD

Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD

(Table 56 on page 97).

20.5

Timer 0 and Timer 1 operating modes

The “Timer” or “Counter” function is selected by the C/T control bits in TMOD. The four

operating modes are selected by bit-pairs M[1:0] in TMOD. Modes 0, 1, and 2 are the same

for both Timer/Counters. Mode 3 is different.

20.5.1

Mode 0

Putting either Timer/Counter into mode 0 makes it an 8-bit Counter with a divide-by-32 pre-

scaler. Figure 21 on page 98 shows mode 0 operation as it applies to Timer 1 (same applies

to Timer 0).

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over

from all '1s' to all '0s,' it sets the Timer Interrupt flag TF1. The counted input is enabled to the

Timer when TR1 = 1 and either GATE = 0 or EXTINT1 = 1. (Setting GATE = 1 allows the

Timer to be controlled by external input pin, EXTINT1, to facilitate pulse width

measurements). TR1 is a control bit in the SFR, TCON. GATE is a bit in the SFR, TMOD.

The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits

of TL1 are indeterminate and should be ignored. Setting the run flag, TR1, does not clear

the registers.

Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, C0, TL0,

TH0, and EXTINT0 for the corresponding Timer 1 signals in Figure 21 on page 98. There

are two different GATE Bits, one for Timer 1 and one for Timer 0.

20.5.2

Mode 1

Mode 1 is the same as mode 0, except that the Timer register is being run with all 16 bits.

20.5.3

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as

shown in Figure 22 on page 98. Overflow from TL1 not only sets TF1, but also reloads TL1

with the contents of TH1, which is preset with firmware. The reload leaves TH1 unchanged.

Mode 2 operation is the same for Timer/Counter 0.

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