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LAN9500AI Datasheet(PDF) 114 Page - Microchip Technology |
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LAN9500AI Datasheet(HTML) 114 Page - Microchip Technology |
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114 / 213 page  LAN950x DS00001875A-page 114 2010 - 2015 Microchip Technology Inc. Figure 6-2 flowcharts PME operation while in Internal PHY mode. The following conditions hold: EEPROM Configuration: • GPIO PME Enable = 1 (enabled) • GPIO PME Configuration = 0 (PME signaled via level on GPIO pin) • GPIO PME Length = 0 (NA) • GPIO PME Polarity = 1 (high level signals event) • GPIO PME Buffer Type = 1 (Push-Pull) • GPIO PME WOL Select = 0 (Magic Packet wakeup) • GPIO10 Detection Select = 0 (Active-low detection) • Power Method = 1 (self powered) • MAC address for Magic Packet PME signaling configuration (as determined by PHY Mode) • GPIO0 signals PME • GPIO1 is PME_MODE_SEL Note: A POR occurring when PME_MODE_SEL = 1 and an EEPROM present with the GPIO PME Enable set results in the device entering PME Mode. |
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